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Disambiguation of "Kolodny, Avinoam"

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Design and modelling of network on chip interconnects using transmission lines.

, , and . ICECS, page 403-406. IEEE, (2004)

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Other publications of authors with the same name

Task Scheduling Based On Thread Essence and Resource Limitations., , and . JCP, 7 (1): 53-64 (2012)Optimal resizing of bus wires in layout migration., , and . ICECS, page 411-414. IEEE, (2004)Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects., , , and . VLSI-SOC, page 99-104. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Quasi Fat Trees for HPC Clouds and Their Fault-Resilient Closed-Form Routing., , and . Hot Interconnects, page 41-48. IEEE Computer Society, (2014)Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing., , and . Integration, (2015)Design and dynamic management of hierarchical NoCs., , and . Microprocessors and Microsystems - Embedded Hardware Design, (2016)Memristor-based IMPLY logic design procedure., , , and . ICCD, page 142-147. IEEE Computer Society, (2011)On-die decoupling capacitance: frequency domain analysis of activity radius., , , and . ISCAS, IEEE, (2006)Crosstalk noise reduction in synthesized digital logic circuits., and . IEEE Trans. VLSI Syst., 11 (6): 1153-1158 (2003)A clock-tuning circuit for system-on-chip., , and . IEEE Trans. VLSI Syst., 11 (4): 616-626 (2003)