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Improving Bounds for FPGA Logic Minimization., , , and . FPT, page 245-248. IEEE, (2007)Runtime assertions and exceptions for streaming systems., and . FPL, page 1-4. IEEE, (2013)Smart technologies for effective reconfiguration: The FASTER approach., , , , , , , , , and 4 other author(s). ReCoSoC, page 1-7. IEEE, (2012)FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration., , , , , , , , , and 5 other author(s). DSD, page 234-241. IEEE Computer Society, (2012)Customizable Composition and Parameterization of Hardware Design Transformations., , , and . DSD, page 595-602. IEEE Computer Society, (2010)Real-time Extensions to a C-like Hardware Description Language., and . FCCM, page 302-304. IEEE Computer Society, (2003)Transparent insertion of latency-oblivious logic onto FPGAs., , and . FPL, page 1-8. IEEE, (2014)EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures., , , , , , , , , and 9 other author(s). ReCoSoC, page 1-7. IEEE, (2016)Using Statistical Assertions to Guide Self-Adaptive Systems., , and . Int. J. Reconfig. Comp., (2014)DeepPump: Multi-pumping deep Neural Networks., , , and . ASAP, page 206. IEEE Computer Society, (2017)