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Test Data Volume Comparison: Monolithic vs. Modular SoC Testing., , , , and . IEEE Design & Test of Computers, 26 (3): 25-37 (2009)Fault Analysis-Based Logic Encryption., , , , , , and . IEEE Trans. Computers, 64 (2): 410-424 (2015)SMART: Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory., , , , and . CoRR, (2019)Test Power Reduction via Deterministic Alignment of Stimulus and Response Bits., , and . J. Low Power Electronics, 7 (4): 573-584 (2011)Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation., and . DFT, page 325-333. IEEE Computer Society, (2002)Regaining Trust in VLSI Design: Design-for-Trust Techniques., , and . Proceedings of the IEEE, 102 (8): 1266-1282 (2014)Rewind-Support for Peak Capture Power Reduction in Launch-Off-Shift Testing.. Asian Test Symposium, page 78-83. IEEE Computer Society, (2011)Provably-Secure Logic Locking: From Theory To Practice., , , , , and . ACM Conference on Computer and Communications Security, page 1601-1618. ACM, (2017)Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing., and . DATE, page 182-187. ACM, (2008)Aggressive Test Power Reduction Through Test Stimuli Transformation., and . ICCD, page 542-547. IEEE Computer Society, (2003)