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Disambiguation of "Pamula, Rajesh"

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An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS.

, , , , , and . VLSI Circuits, page 1-2. IEEE, (2018)

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A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains., , , , , , , and . J. Solid-State Circuits, 54 (4): 1173-1184 (2019)An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor., , , , , , , and . VLSI Circuits, page 65-66. IEEE, (2018)Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS., , , , and . ISSCC, page 312-314. IEEE, (2019)An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS., , , , , and . VLSI Circuits, page 1-2. IEEE, (2018)Architecture Considerations for Stochastic Computing Accelerators., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 37 (11): 2277-2289 (2018)Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS., , and . J. Solid-State Circuits, 55 (2): 494-504 (2020)A 172 µW Compressively Sampled Photoplethysmographic (PPG) Readout ASIC With Heart Rate Estimation Directly From Compressively Sampled Data., , , , , , , and . IEEE Trans. Biomed. Circuits and Systems, 11 (3): 487-496 (2017)A 680 nA ECG Acquisition IC for Leadless Pacemaker Applications., , , , , , , and . IEEE Trans. Biomed. Circuits and Systems, 8 (6): 779-786 (2014)A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS., , , , , and . ESSCIRC, page 77-80. IEEE, (2019)A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor., , , , , , and . ISSCC, page 302-304. IEEE, (2018)