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Disambiguation of "Sathe, Visvesh S."

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An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS.

, , , , , and . VLSI Circuits, page 1-2. IEEE, (2018)

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S. Schumann

S. Seemann

S. Wartzack

Boettinger S

S. Toro

 

Other publications of authors with the same name

A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains., , , , , , , and . J. Solid-State Circuits, 54 (4): 1173-1184 (2019)Resonant-Clock Latch-Based Design., , and . J. Solid-State Circuits, 43 (4): 864-873 (2008)An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor., , , , , , , and . VLSI Circuits, page 65-66. IEEE, (2018)Energy-Efficient GHz-Class Charge-Recovery Logic., , and . J. Solid-State Circuits, 42 (1): 38-47 (2007)A GHz-class charge recovery logic., , and . ISLPED, page 91-94. ACM, (2005)Boost Logic: A High Speed Energy Recovery Circuit Family., , and . ISVLSI, page 22-27. IEEE Computer Society, (2005)Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control., , , , , , and . IEEE J. Solid State Circuits, 57 (1): 90-102 (2022)Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors., , , , , and . IEEE Trans. on Circuits and Systems, 65-I (12): 4285-4298 (2018)Introduction to the Special Section on the 2015 Custom Integrated Circuits Conference., and . J. Solid-State Circuits, 51 (8): 1733 (2016)Exploiting Electrocorticographic Spectral Characteristics for Optimized Signal Chain Design: A 1.08 Analog Front End With Reduced ADC Resolution Requirements., , , , and . IEEE Trans. Biomed. Circuits and Systems, 10 (6): 1171-1180 (2016)