%0 Conference Paper %1 conf/vlsic/PamulaSKRZS18 %A Pamula, Rajesh %A Sun, Xun %A Kim, Sung %A ur Rahman, Fahim %A Zhang, Baosen %A Sathe, Visvesh S. %B VLSI Circuits %D 2018 %I IEEE %K dblp %P 1-2 %T An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2018.html#PamulaSKRZS18 %@ 978-1-5386-4214-6

@inproceedings{conf/vlsic/PamulaSKRZS18, added-at = {2019-10-30T00:00:00.000+0100}, author = {Pamula, Rajesh and Sun, Xun and Kim, Sung and ur Rahman, Fahim and Zhang, Baosen and Sathe, Visvesh S.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2b7252a47357a2b9361130e6bb9b5fcf8/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2018}, ee = {https://doi.org/10.1109/VLSIC.2018.8502375}, interhash = {133db7061327823cde9eacd8c23f6b1f}, intrahash = {b7252a47357a2b9361130e6bb9b5fcf8}, isbn = {978-1-5386-4214-6}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2019-11-02T11:33:51.000+0100}, title = {An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2018.html#PamulaSKRZS18}, year = 2018 }