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Disambiguation of "Pedram, Massoud"

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Architectures for Silicon Nanoelectronics and Beyond.

, , , , , , , and . IEEE Computer, 40 (1): 25-33 (2007)

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Seyed Pedram Hosseyni Damabi University of Stuttgart

 

Other publications of authors with the same name

Forecasting-Based Dynamic Virtual Channel Management for Power Reduction in Network-on-Chips., , , and . J. Low Power Electronics, 5 (3): 385-395 (2009)Predictive-Flow-Queue-Based Energy Optimization for Gigabit Ethernet Controllers., , and . IEEE Trans. VLSI Syst., 17 (8): 1113-1126 (2009)Fast Interconnect and Gate Timing Analysis for Performance Optimization., , , and . IEEE Trans. VLSI Syst., 14 (12): 1383-1388 (2006)Performance Comparisons Between 7-nm FinFET and Conventional Bulk CMOS Standard Cell Libraries., , , , , and . IEEE Trans. on Circuits and Systems, 62-II (8): 761-765 (2015)Interconnect energy dissipation in high-speed ULSI circuits., , and . IEEE Trans. on Circuits and Systems, 51-I (8): 1501-1514 (2004)Formal Verification Using Edge-Valued Binary Decision Diagrams., , and . IEEE Trans. Computers, 45 (2): 247-255 (1996)Architectures for Silicon Nanoelectronics and Beyond., , , , , , , and . IEEE Computer, 40 (1): 25-33 (2007)Accurate Modeling of the Delay and Energy Overhead of Dynamic Voltage and Frequency Scaling in Modern Microprocessors., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (5): 695-708 (2013)Charge Recycling in Power-Gated CMOS Circuits., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (10): 1798-1811 (2008)Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 24 (1): 18-28 (2005)