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Logical Time at Work: Capturing Data Dependencies and Platform Constraints., , and . FDL, page 241-. ECSI, Electronic Chips & Systems design Initiative, (2010)A MDA Approach for Systems Dedicated to Process Control., and . RTCSA, page 567-570. IEEE Computer Society, (2005)A MDA-based approach for real time embedded systems simulation., and . DS-RT, page 257-264. IEEE Computer Society, (2005)The clock constraint specification language for building timed causality models - Application to synchronous data flow graphs., , , and . ISSE, 6 (1-2): 99-106 (2010)Towards a meta-language for the concurrency concern in DSLs., , , , and . DATE, page 313-316. ACM, (2015)Supporting the Engineering of Multi-Fidelity Simulation Units With Simulation Goals., , and . MoDELS (Companion), page 317-321. IEEE, (2021)Towards Formal System Modeling: Making Explicit and Formal the Concurrent and Timed Operational Semantics to Better Understand Heterogeneous Models.. (2019)VHDL Observers for Clock Constraint Checking., , and . SIES, page 98-107. IEEE, (2010)A Timing Model for Specifying Multi Clock Automotive Systems: The Timing Augmented Description Language V2., , , and . ICECCS, page 230-239. IEEE Computer Society, (2012)Executing AADL Models with UML/MARTE., , and . ICECCS, page 371-376. IEEE Computer Society, (2009)