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Disambiguation of "Ying, Haoyuan"

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Deadlock-free routing algorithms for 3-dimension Networks-on-Chip with reduced vertical channel density topologies.

, , and . HPCS, page 268-274. IEEE, (2012)

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Tzu-Ying Chen University of Stuttgart

 

Other publications of authors with the same name

Invited paper: Design criteria for dependable System-on-Chip architectures., , , , , and . ReCoSoC, page 1-6. IEEE, (2011)GSNOC UI - A comfortable graphical user interface for advanced design and evaluation of 3-dimensional scalable Networks-on-Chip., , and . HPCS, page 261-267. IEEE, (2012)A hardware/software co-design reconfigurable Network-on-Chip FPGA emulation method., , and . ReCoSoC, page 1-8. IEEE, (2014)Deadlock-free routing algorithms for 3-dimension Networks-on-Chip with reduced vertical channel density topologies., , and . HPCS, page 268-274. IEEE, (2012)GSNoC - The comprehensive design platform for 3-dimensional Networks-on-Chip based many core embedded systems., , and . HPCS, page 217-223. IEEE, (2013)A simulation framework for 3-dimension Networks-on-chip with different vertical channel density configurations., , , , and . DDECS, page 83-88. IEEE, (2012)NoCDepend: A Flexible and Scalable Dependability Technique for 3D Networks-on-Chip., , , , and . DDECS, page 75-78. IEEE Computer Society, (2015)Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip., , and . ReCoSoC, page 1-6. IEEE, (2012)LatEst: Latency estimation and high speed evaluation for wormhole switched Networks-on-Chip., , , and . ReCoSoC, page 1-7. IEEE, (2014)Deadlock-free generic routing algorithms for 3-dimensional Networks-on-Chip with reduced vertical link density topologies., , , and . Journal of Systems Architecture - Embedded Systems Design, 59 (7): 528-542 (2013)