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Disambiguation of "Jaiswal, Ashok"

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Deadlock-free routing algorithms for 3-dimension Networks-on-Chip with reduced vertical channel density topologies.

, , and . HPCS, page 268-274. IEEE, (2012)

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Deadlock-free routing algorithms for 3-dimension Networks-on-Chip with reduced vertical channel density topologies., , and . HPCS, page 268-274. IEEE, (2012)A low-jitter clock and data recovery for GDDR5 interface trainings., , , and . ICICDT, page 1-4. IEEE, (2014)Invited paper: Design criteria for dependable System-on-Chip architectures., , , , , and . ReCoSoC, page 1-6. IEEE, (2011)Transmitter equalizer training based on pilot signal and peak detection., , , and . ICECS, page 377-380. IEEE, (2013)Adaptive Low-Power Synchronization Technique for Multiple Source-Synchronous Clocks in High-Speed Communication Systems., , , and . DSD, page 752-758. IEEE Computer Society, (2013)Deadlock-free generic routing algorithms for 3-dimensional Networks-on-Chip with reduced vertical link density topologies., , , and . Journal of Systems Architecture - Embedded Systems Design, 59 (7): 528-542 (2013)Adaptive Equalizer Training for High-Speed Low-Power Communication Systems., , , , and . DSD, page 745-751. IEEE Computer Society, (2013)Low-power signal integrity trainings for multi-clock source-synchronous memory systems., , and . SoCC, page 319-324. IEEE, (2013)Low-power design of hybrid digital impedance calibration for process, voltage, temperature compensations., , , and . ICECS, page 37-40. IEEE, (2013)Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes., , , and . SoCC, page 5-10. IEEE, (2014)