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A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches., , , and . IEEE Micro, 34 (3): 80-90 (2014)Achieving Exascale Capabilities through Heterogeneous Computing., , , , , , , , , and . IEEE Micro, 35 (4): 26-36 (2015)Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap., and . IEEE Micro, 32 (3): 70-78 (2012)PEEP: Exploiting predictability of memory dependences in SMT processors., , and . HPCA, page 137-148. IEEE Computer Society, (2008)Store vectors for scalable memory dependence prediction and scheduling., and . HPCA, page 65-76. IEEE Computer Society, (2006)Width-Partitioned Load Value Predictors.. J. Instruction-Level Parallelism, (2003)Exploiting Bias in the Hysteresis Bit of 2-bit Saturating Counters in Branch Predictors., , and . J. Instruction-Level Parallelism, (2003)Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories., , , , , and . HPCA, page 126-136. IEEE Computer Society, (2015)Machine learning for performance and power modeling of heterogeneous systems., and . ICCAD, page 47. ACM, (2018)There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes., , , , , and . ISCA, page 678-690. ACM, (2017)