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Guest Editorial New Interconnect Technologies in On-Chip Communication., , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (2): 121-123 (2012)Exploiting New Interconnect Technologies in On-Chip Communication., , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (2): 124-136 (2012)Revisiting the performance impact of branch predictor latencies.. ISPASS, page 59-69. IEEE Computer Society, (2006)A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch., , , , and . MICRO, page 247-257. IEEE Computer Society, (2012)Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors., and . SBAC-PAD, page 55-62. IEEE Computer Society, (2006)A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate., , , , , , , and . Parallel Computing, (2016)The impact of 3-dimensional integration on the design of arithmetic units., and . ISCAS, IEEE, (2006)Exploiting Interposer Technologies to Disintegrate and Reintegrate Multicore Processors., , and . IEEE Micro, 36 (3): 84-93 (2016)Die Stacking (3D) Microarchitecture., , , , , , , , , and 5 other author(s). MICRO, page 469-479. IEEE Computer Society, (2006)Adaptive Caches: Effective Shaping of Cache Behavior to Workloads., , and . MICRO, page 385-396. IEEE Computer Society, (2006)