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A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology.

, , , , , , , , , , , , , and . ESSCIRC, page 303-307. IEEE, (2017)

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A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor., , , , , , , , , and 3 other author(s). ISSCC, page 344-345. IEEE, (2010)Electronic packaging of the IBM System z196 enterprise-class server processor cage., , , , , , , , , and 7 other author(s). IBM Journal of Research and Development, 56 (1): 2 (2012)Characterization of a 0.13 mum CMOS Link Chip using Time Resolved Emission (TRE)., , , , , , and . Microelectronics Reliability, 45 (9-11): 1550-1553 (2005)Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V., , , , , , , , , and 2 other author(s). ISSCC, page 322-606. IEEE, (2007)Testing the Enterprise IBM System/390TM Multi Processor., , , and . ITC, page 115-123. IEEE Computer Society, (1997)A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction., , , , , , , and . ESSCIRC, page 343-346. IEEE, (2015)Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 43 (1): 163-171 (2008)A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology., , , , , , , , , and 4 other author(s). ESSCIRC, page 303-307. IEEE, (2017)26.2 Power supply noise in a 22nm z13™ microprocessor., , , , , , , , , and 5 other author(s). ISSCC, page 438-439. IEEE, (2017)