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Joint Equalization and Coding for On-Chip Bus Communication., , and . IEEE Trans. VLSI Syst., 16 (3): 314-318 (2008)System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near-Vt Computing., , and . IEEE Trans. on Circuits and Systems, 61-II (9): 726-730 (2014)Low-power reconfigurable signal processing via dynamic algorithm transformations (DAT)., and . ICASSP, page 3081-3084. IEEE, (1998)Design methodology for high-speed iterative decoder architectures., and . ICASSP, page 3085-3088. IEEE, (2002)An improved systolic architecture for 2-D digital filters.. IEEE Trans. Signal Processing, 39 (5): 1195-1202 (1991)Linear turbo equalization analysis via BER transfer and EXIT charts., , and . IEEE Trans. Signal Processing, 53 (8-1): 2883-2897 (2005)A pipelined adaptive NEXT canceller., and . IEEE Trans. Signal Processing, 46 (8): 2252-2258 (1998)A Study of BER-Optimal ADC-Based Receiver for Serial Links., , , , , , and . IEEE Trans. on Circuits and Systems, 63-I (5): 693-704 (2016)A sphere decoding approach for the vector Viterbi algorithm., , , and . ACSCC, page 114-118. IEEE, (2012)Error resilient MRF message passing architecture for stereo matching., , , and . SiPS, page 348-353. IEEE, (2013)