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Disambiguation of "Balamurugan, Ganesh"

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Joint Equalization and Coding for On-Chip Bus Communication.

, , and . IEEE Trans. VLSI Syst., 16 (3): 314-318 (2008)

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Ganesh Deepak Rupakula University of Stuttgart

 

Other publications of authors with the same name

A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS., , , , , , and . VLSIC, page 346-. IEEE, (2015)Joint Equalization and Coding for On-Chip Bus Communication., , and . IEEE Trans. VLSI Syst., 16 (3): 314-318 (2008)A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS., , , , , , , , , and . ISSCC, page 402-403. IEEE, (2013)Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver., , , , , , , , and . IEEE Trans. on Circuits and Systems, 56-I (8): 1818-1829 (2009)A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS., , , and . ESSCIRC, page 238-241. IEEE, (2018)Energy-efficient dynamic circuit design in the presence of crosstalk noise., and . ISLPED, page 24-29. ACM, (1999)A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS., , , , , , , , , and . J. Solid-State Circuits, 48 (12): 3229-3242 (2013)A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS., , , , , , , , , and 6 other author(s). J. Solid-State Circuits, 49 (12): 3079-3090 (2014)Strong injection locking of low-Q LC oscillators., , , , , , , and . CICC, page 699-702. IEEE, (2008)Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links., and . ICCD, page 254-260. IEEE Computer Society, (2003)