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Cost-efficient hardware implementation of stereo image depth optimization system.

, , , and . IC3D, page 1-6. IEEE, (2014)

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A high dynamic range programmable gain amplifier for HomePlug AV powerline communication system., , and . ISCAS, page 2715-2718. IEEE, (2013)A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS., , , and . ISSCC, page 244-246. IEEE, (2012)Future SoC Design Challenges and Solutions (invited)., and . ISQED, page 534-538. IEEE Computer Society, (2002)Linear Time Hierarchical Capacitance Extraction without Multipole Expansion., , , , and . ICCD, page 98-103. IEEE Computer Society, (2001)An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example., , , and . IEEE Trans. on Circuits and Systems, 59-I (8): 1644-1655 (2012)SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design., and . ASP-DAC, page 559-564. IEEE Computer Society, (2007)Realizable Reduction for Electromagnetically Coupled RLMC Interconnects., and . DATE, page 1400-1401. IEEE Computer Society, (2004)PODEA: Power delivery efficient analysis with realizable model reduction., , and . ISCAS (4), page 608-611. IEEE, (2003)A fast-settling high linearity auto gain control for broadband OFDM-based PLC system., , , and . ISCAS, page 2852-2855. IEEE, (2015)Current-mode adaptively hysteretic control for buck converters with fast transient response and improved output regulation., , , , , and . ISCAS, page 950-953. IEEE, (2014)