PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Chen, Charlie Chung-Ping"

Author of the publication

copydeleteadd this publication to your clipboard
A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS.

, , , and . ISSCC, page 244-246. IEEE, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Charlie Sheen

Hong Chen University of Stuttgart

Phi-Long Chung University of Stuttgart

Yiyin Chen University of Stuttgart

Jun Chen University of Stuttgart

 

Other publications of authors with the same name

Linear Time Hierarchical Capacitance Extraction without Multipole Expansion., , , , and . ICCD, page 98-103. IEEE Computer Society, (2001)Future SoC Design Challenges and Solutions (invited)., and . ISQED, page 534-538. IEEE Computer Society, (2002)PODEA: Power delivery efficient analysis with realizable model reduction., , and . ISCAS (4), page 608-611. IEEE, (2003)SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design., and . ASP-DAC, page 559-564. IEEE Computer Society, (2007)A high dynamic range programmable gain amplifier for HomePlug AV powerline communication system., , and . ISCAS, page 2715-2718. IEEE, (2013)Realizable Reduction for Electromagnetically Coupled RLMC Interconnects., and . DATE, page 1400-1401. IEEE Computer Society, (2004)Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (6): 1183-1191 (2006)A fast-settling high linearity auto gain control for broadband OFDM-based PLC system., , , and . ISCAS, page 2852-2855. IEEE, (2015)Current-mode adaptively hysteretic control for buck converters with fast transient response and improved output regulation., , , , , and . ISCAS, page 950-953. IEEE, (2014)A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme., , , , , and . ISCAS, page 2393-2396. IEEE, (2015)