%0 Journal Article %1 journals/cal/ChenCWY17 %A Chen, Li-Jhan %A Cheng, Hsiang-Yun %A Wang, Po-Han %A Yang, Chia-Lin %D 2017 %J IEEE Comput. Archit. Lett. %K dblp %N 2 %P 127-131 %T Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling. %U http://dblp.uni-trier.de/db/journals/cal/cal16.html#ChenCWY17 %V 16

@article{journals/cal/ChenCWY17, added-at = {2020-03-15T00:00:00.000+0100}, author = {Chen, Li-Jhan and Cheng, Hsiang-Yun and Wang, Po-Han and Yang, Chia-Lin}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/26a6f18efc76e5efc6286563f8ebdde5a/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/LCA.2017.2693371}, interhash = {52f537cc3cac558308dacded034f6ef6}, intrahash = {6a6f18efc76e5efc6286563f8ebdde5a}, journal = {IEEE Comput. Archit. Lett.}, keywords = {dblp}, number = 2, pages = {127-131}, timestamp = {2020-04-20T12:49:55.000+0200}, title = {Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling.}, url = {http://dblp.uni-trier.de/db/journals/cal/cal16.html#ChenCWY17}, volume = 16, year = 2017 }