Zusammenfassung
In communication systems, autoencoder refers to a system that replaces parts of the traditional transmitter and receiver of the baseband processing chain with artificial neural networks (ANNs). This allows to jointly train the system for an underlying channel model by reconstructing the input symbols at the output. Since the actual behavior of a real communication channel cannot be perfectly reproduced by an abstract model, it is necessary for the autoencoder to adapt to the changing conditions at runtime. Thus, online fine-tuning, in the form of ANN-retraining is of great importance. A platform able to satisfy the low-latency and low-power requirements of embedded communication systems are Field-programmable gate arrays (FPGAs). In this paper, we present an online-trainable low-power FPGA architecture for the receiver of an autoencoder-based communication chain. The architecture is embedded into an exploration framework that automatically determines the optimal degree of parallelism to minimize latency or power consumption. Our solutions achieve 2000×higher throughput than a high-performance GPU, draw 5×less power than an embedded CPU and are 5800×more energy efficient compared to an embedded GPU, for a batch size of one. To the best of our knowledge, this is the first FPGA-based autoencoder implementation for communication systems.
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