%0 Conference Paper %1 conf/itc/BaileyMSTWFAWR02 %A Bailey, B. %A Metayer, A. %A Svrcek, B. %A Tendolkar, Nandu %A Wolf, E. %A Fiene, Eric %A Alexander, Mike %A Woltenberg, Rick %A Raina, Rajesh %B ITC %D 2002 %I IEEE Computer Society %K dblp %P 574-583 %T Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. %U http://dblp.uni-trier.de/db/conf/itc/itc2002.html#BaileyMSTWFAWR02 %@ 0-7803-7543-2

@inproceedings{conf/itc/BaileyMSTWFAWR02, added-at = {2015-08-26T00:00:00.000+0200}, author = {Bailey, B. and Metayer, A. and Svrcek, B. and Tendolkar, Nandu and Wolf, E. and Fiene, Eric and Alexander, Mike and Woltenberg, Rick and Raina, Rajesh}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/27c4ace69b6dfa72a8af8fe4647b46aee/dblp}, booktitle = {ITC}, crossref = {conf/itc/2002}, ee = {http://doi.ieeecomputersociety.org/10.1109/TEST.2002.1041808}, interhash = {ee51e79233e85d09fc6837a9a05e8e71}, intrahash = {7c4ace69b6dfa72a8af8fe4647b46aee}, isbn = {0-7803-7543-2}, keywords = {dblp}, pages = {574-583}, publisher = {IEEE Computer Society}, timestamp = {2016-02-02T15:32:05.000+0100}, title = {Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture.}, url = {http://dblp.uni-trier.de/db/conf/itc/itc2002.html#BaileyMSTWFAWR02}, year = 2002 }