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Disambiguation of "Raina, Rajesh"

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Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture.

, , , , , , , , and . ITC, page 574-583. IEEE Computer Society, (2002)

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Other publications of authors with the same name

Design-for-test methodology for Motorola PowerPC microprocessors., and . ITC, page 810-819. IEEE Computer Society, (1999)DFT advances in Motorola's Next-Generation 74xx PowerPCTM microprocessor., , , , , , and . ITC, page 131-140. IEEE Computer Society, (2000)Jitter measurements of a PowerPCTM microprocessor using an analytic signal method., , , , , , and . ITC, page 955-964. IEEE Computer Society, (2000)Skew measurements in clock distribution circuits using an analytic signal method., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 23 (7): 997-1009 (2004)Testing clock distribution circuits using an analytic signal method., , , , , and . ITC, page 323-331. IEEE Computer Society, (2001)Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor ., , , , , and . ITC, page 1111-1119. IEEE Computer Society, (2002)Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture., , , , , and . VTS, page 3-8. IEEE Computer Society, (2002)At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor., , , and . VTS, page 3-8. IEEE Computer Society, (2000)DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor., , , , , , , and . ITC, page 137-146. IEEE Computer Society, (1999)A Wavelet-Based Timing Parameter Extraction Method., , , and . ITC, page 120-128. IEEE Computer Society, (2002)