%0 Conference Paper %1 conf/fpl/MaheshwariMSK16 %A Maheshwari, Sidharth %A Modi, Gourav %A Siddhartha, %A Kapre, Nachiket %B FPL %D 2016 %E Ienne, Paolo %E Najjar, Walid A. %E Anderson, Jason %E Brisk, Philip %E Stechele, Walter %I IEEE %K dblp %P 1-4 %T Vector FPGA acceleration of 1-D DWT computations using sparse matrix skeletons. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2016.html#MaheshwariMSK16 %@ 978-2-8399-1844-2

@inproceedings{conf/fpl/MaheshwariMSK16, added-at = {2016-10-04T00:00:00.000+0200}, author = {Maheshwari, Sidharth and Modi, Gourav and Siddhartha and Kapre, Nachiket}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2d1d71732715660f9450a49089ac2dc4f/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2016}, editor = {Ienne, Paolo and Najjar, Walid A. and Anderson, Jason and Brisk, Philip and Stechele, Walter}, ee = {http://dx.doi.org/10.1109/FPL.2016.7577361}, interhash = {ecd03f116cc33c5c1abecddac3887b54}, intrahash = {d1d71732715660f9450a49089ac2dc4f}, isbn = {978-2-8399-1844-2}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2016-10-05T09:34:11.000+0200}, title = {Vector FPGA acceleration of 1-D DWT computations using sparse matrix skeletons.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2016.html#MaheshwariMSK16}, year = 2016 }