%0 Conference Paper %1 conf/ats/AsadaWHMKKSWQ15 %A Asada, K. %A Wen, Xiaoqing %A Holst, Stefan %A Miyase, Kohei %A Kajihara, Seiji %A Kochte, Michael A. %A Schneider, Eric %A Wunderlich, Hans-Joachim %A Qian, J. %B ATS %D 2015 %I IEEE Computer Society %K dblp %P 103-108 %T Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. %U http://dblp.uni-trier.de/db/conf/ats/ats2015.html#AsadaWHMKKSWQ15 %@ 978-1-4673-9739-1

@inproceedings{conf/ats/AsadaWHMKKSWQ15, added-at = {2016-04-14T00:00:00.000+0200}, author = {Asada, K. and Wen, Xiaoqing and Holst, Stefan and Miyase, Kohei and Kajihara, Seiji and Kochte, Michael A. and Schneider, Eric and Wunderlich, Hans-Joachim and Qian, J.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2709b5eb912ce3c23fb426c5ac37cd5d1/dblp}, booktitle = {ATS}, crossref = {conf/ats/2015}, ee = {http://doi.ieeecomputersociety.org/10.1109/ATS.2015.25}, interhash = {503478c4c4c663030c7267cacda3d358}, intrahash = {709b5eb912ce3c23fb426c5ac37cd5d1}, isbn = {978-1-4673-9739-1}, keywords = {dblp}, pages = {103-108}, publisher = {IEEE Computer Society}, timestamp = {2016-04-15T09:32:35.000+0200}, title = {Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch.}, url = {http://dblp.uni-trier.de/db/conf/ats/ats2015.html#AsadaWHMKKSWQ15}, year = 2015 }