%0 Conference Paper %1 conf/vlsid/DevanathanBP15 %A Devanathan, V. R. %A Balasubramanian, Lakshmanan %A Parekhji, Rubin A. %B VLSI Design %D 2015 %I IEEE Computer Society %K dblp %P 363-368 %T New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2015.html#DevanathanBP15 %@ 978-1-4799-6658-5

@inproceedings{conf/vlsid/DevanathanBP15, added-at = {2015-04-20T00:00:00.000+0200}, author = {Devanathan, V. R. and Balasubramanian, Lakshmanan and Parekhji, Rubin A.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/235b6507ee21ee104ffbaca1d30e3cb49/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2015}, ee = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2015.67}, interhash = {4351a1a0e45c55f80f7b5294f3832005}, intrahash = {35b6507ee21ee104ffbaca1d30e3cb49}, isbn = {978-1-4799-6658-5}, keywords = {dblp}, pages = {363-368}, publisher = {IEEE Computer Society}, timestamp = {2016-02-02T11:08:47.000+0100}, title = {New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2015.html#DevanathanBP15}, year = 2015 }