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Disambiguation of "Devanathan, V. R."

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New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation.

, , and . VLSI Design, page 363-368. IEEE Computer Society, (2015)

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R. Koerner

R. Watty

V. Vaikuntanathan

V. Zaverkin

Univ. -Prof. Dr. Joris van Slageren University of Stuttgart

Electrocatalytic proton reduction: Metal based fused diporphyrins with proton relays for efficient catalysis, , , , , , , , and . Dataset, (2024)Related to: Chandra, S., Singha Hazari, A., Song, Q., Hunger, D., Neuman, N. I., van Slageren, J., Klemm, E. & Sarkar, B. (2023). Remarkable Enhancement of Catalytic Activity of Cu-Complexes in the Electrochemical Hydrogen Evolution Reaction by Using Triply Fused Porphyrin. ChemSusChem 16, e202201146. doi: 10.1002/cssc.202201146.
 

Other publications of authors with the same name

Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications., , , and . J. Low Power Electronics, 11 (2): 133-148 (2015)Variation-Tolerant, Power-Safe Pattern Generation., , and . IEEE Design & Test of Computers, 24 (4): 374-384 (2007)Towards adaptive test of multi-core RF SoCs., , , , , and . DATE, page 743-748. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Towards effective and compression-friendly test of memory interface logic., , , and . ITC, page 124-133. IEEE Computer Society, (2010)A Framework for Concurrency Control in Real-Time Distributed Collaboration for Mobile Systems., , and . ICDCS Workshops, page 488-492. IEEE Computer Society, (2003)ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs., , , , and . VLSI Design, page 342-347. IEEE Computer Society, (2014)Interactive presentation: On power-profiling and pattern generation for power-safe scan tests., , and . DATE, page 534-539. EDA Consortium, San Jose, CA, USA, (2007)Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage.. Asian Test Symposium, page 300-305. IEEE Computer Society, (2005)Methodology for low power test pattern generation using activity threshold control logic., , and . ICCAD, page 526-529. IEEE Computer Society, (2007)A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction., , , and . J. Low Power Electronics, 4 (1): 101-110 (2008)