%0 Journal Article %1 journals/vlsi/ChoiKC01 %A Choi, Jung Yun %A Kim, Young Hwan %A Cho, Kyoung-Rok %D 2001 %J VLSI Design %K dblp %N 2 %P 221-231 %T Backward Propagated Capacitance Model for Register Transfer Level Power Estimation. %U http://dblp.uni-trier.de/db/journals/vlsi/vlsi2001.html#ChoiKC01 %V 2001

@article{journals/vlsi/ChoiKC01, added-at = {2018-08-16T00:00:00.000+0200}, author = {Choi, Jung Yun and Kim, Young Hwan and Cho, Kyoung-Rok}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/278d23cf944a6c316a3329449e1e9641c/dblp}, ee = {https://doi.org/10.1155/2001/78456}, interhash = {3d469ef20046f217c2d3a24d03d53411}, intrahash = {78d23cf944a6c316a3329449e1e9641c}, journal = {VLSI Design}, keywords = {dblp}, number = 2, pages = {221-231}, timestamp = {2019-09-27T06:27:54.000+0200}, title = {Backward Propagated Capacitance Model for Register Transfer Level Power Estimation.}, url = {http://dblp.uni-trier.de/db/journals/vlsi/vlsi2001.html#ChoiKC01}, volume = 2001, year = 2001 }