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%0 Conference Paper
%1 conf/eurodac/AcostaBVBH93
%A Acosta, Antonio J.
%A Barros, Angel Barriga
%A Valencia, Manuel
%A Bellido, Manuel J.
%A Huertas, José L.
%B EURO-DAC
%D 1993
%I IEEE Computer Society
%K dblp
%P 460-465
%T Modeling of real bistables in VHDL.
%U http://dblp.uni-trier.de/db/conf/eurodac/euro-dac1993.html#AcostaBVBH93
%@ 0-8186-4350-1
@inproceedings{conf/eurodac/AcostaBVBH93,
added-at = {2015-11-16T00:00:00.000+0100},
author = {Acosta, Antonio J. and Barros, Angel Barriga and Valencia, Manuel and Bellido, Manuel J. and Huertas, José L.},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2ea5004c271d89f51785825c2a9f5d12d/dblp},
booktitle = {EURO-DAC},
crossref = {conf/eurodac/1993},
ee = {http://dx.doi.org/10.1109/EURDAC.1993.410677},
interhash = {13f9ca4a1a89c3ebe9859fd37970489f},
intrahash = {ea5004c271d89f51785825c2a9f5d12d},
isbn = {0-8186-4350-1},
keywords = {dblp},
pages = {460-465},
publisher = {IEEE Computer Society},
timestamp = {2016-02-02T14:57:06.000+0100},
title = {Modeling of real bistables in VHDL.},
url = {http://dblp.uni-trier.de/db/conf/eurodac/euro-dac1993.html#AcostaBVBH93},
year = 1993
}
