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PRET DRAM controller: bank privatization for predictability and temporal isolation.

, , , , and . CODES+ISSS, page 99-108. ACM, (2011)

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Abstract state machines as an intermediate representation for high-level synthesis., and . DATE, page 1406-1411. IEEE, (2011)Low cost permanent fault detection using ultra-reduced instruction set co-processors., , and . DATE, page 933-938. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Towards a Multi-MoC Hardware/Software Co-design Framework Using Abstract State Machines., and . MTV, page 53-58. IEEE Computer Society, (2010)CARH: service-oriented architecture for validating system-level designs., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (8): 1458-1474 (2006)synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (10): 1508-1521 (2012)SystemCXML: An Exstensible SystemC Front end Using XML., , , , and . FDL, page 405-409. ECSI, (2005)Model-Driven Validation of SystemC Designs., and . EURASIP J. Emb. Sys., (2008)SCGPSim: a fast SystemC simulator on GPUs., , , and . ASP-DAC, page 149-154. IEEE, (2010)Exploring power management in multi-core systems., , , , , , , , , and 1 other author(s). ASP-DAC, page 708-713. IEEE, (2008)Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow models., and . ACM Great Lakes Symposium on VLSI, page 248-253. ACM, (2004)