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High-Level Synthesis with Variable-Latency Components.

, , and . VLSI Design, page 220-227. IEEE Computer Society, (2000)

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TAO: regular expression-based register-transfer level testability analysis and optimization., , and . IEEE Trans. VLSI Syst., 9 (6): 824-832 (2001)Integrating variable-latency components into high-level synthesis., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 19 (10): 1105-1117 (2000)High-Level Synthesis with Variable-Latency Components., , and . VLSI Design, page 220-227. IEEE Computer Society, (2000): Reducing test application time in high-level test generation., , and . ITC, page 829-838. IEEE Computer Society, (2000)High-level energy macromodeling of embedded software., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 21 (9): 1037-1050 (2002)Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips., , , and . DAC, page 513-518. ACM, (2000)Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions., , and . DAC, page 108-113. ACM Press, (1998)Memory binding for performance optimization of control-flow intensive behaviors., , and . ICCAD, page 482-488. IEEE Computer Society, (1999)Input space-adaptive optimization for embedded-software synthesis., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 24 (11): 1677-1693 (2005)Common-case computation: a high-level energy and performance optimization technique., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 23 (1): 33-49 (2004)