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Integrating Loop and Data Transformations for Global Optimization., and . J. Parallel Distrib. Comput., 62 (4): 563-590 (2002)An Empirical Architecture-Centric Approach to Microarchitectural Design Space Exploration., , and . IEEE Trans. Computers, 60 (10): 1445-1458 (2011)Obituary: Peter Knijnenburg (1961-2007)., and . Concurrency and Computation: Practice and Experience, 21 (1): 5 (2009)The effect of cache models on iterative compilation for combined tiling and unrolling., , , and . Concurrency and Computation: Practice and Experience, 16 (2-3): 247-270 (2004)A hierarchical locality algorithm for NUMA compilation.. PDP, page 106-113. IEEE Computer Society, (1995)Automatic and Portable Mapping of Data Parallel Programs to OpenCL for GPU-Based Heterogeneous Systems., , and . TACO, 11 (4): 42:1-42:26 (2014)Exploring the limits of early register release: Exploiting compiler analysis., , , , and . TACO, 6 (3): 12:1-12:30 (2009)Automatic feature generation for machine learning-based optimising compilation., , and . TACO, 11 (1): 14:1-14:32 (2014)Four Metrics to Evaluate Heterogeneous Multicores., , and . TACO, 12 (4): 37:1-37:25 (2016)IATAC: a smart predictor to turn-off L2 cache lines., , , and . TACO, 2 (1): 55-77 (2005)