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The effect of cache models on iterative compilation for combined tiling and unrolling.

, , , and . Concurrency and Computation: Practice and Experience, 16 (2-3): 247-270 (2004)

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Integrating Loop and Data Transformations for Global Optimization., and . J. Parallel Distrib. Comput., 62 (4): 563-590 (2002)Special Issue: 10th International Workshop on Compilers for Parallel Computers (CPC 2003).. Concurrency and Computation: Practice and Experience, 18 (11): 1333-1334 (2006)The effect of cache models on iterative compilation for combined tiling and unrolling., , , and . Concurrency and Computation: Practice and Experience, 16 (2-3): 247-270 (2004)Statistical Selection of Compiler Options., , , and . MASCOTS, page 494-501. IEEE Computer Society, (2004)A Note on the Smyth Powerdomain Construction.. Fundam. Inform., 26 (2): 133-139 (1996)On the impact of data input sets on statistical compiler tuning., , and . IPDPS, IEEE, (2006)On the Problem of Minimizing Workload Execution Time in SMT Processors., , , , , and . ICSAMOS, page 66-73. IEEE, (2007)Implicit vs. Explicit Resource Allocation in SMT Processors., , , , , and . DSD, page 44-51. IEEE Computer Society, (2004)Automatic Selection of Compiler Options Using Non-parametric Inferential Statistics., , and . IEEE PACT, page 123-132. IEEE Computer Society, (2005)Code Size Reduction by Compiler Tuning., , and . SAMOS, volume 4017 of Lecture Notes in Computer Science, page 186-195. Springer, (2006)