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Disambiguation of "Wu, Chang"

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Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only).

, , , , , , and . FPGA, page 276. ACM, (2015)

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Jingcheng Wu University of Stuttgart

Hanchuan Wu University of Stuttgart

Yongxiang Wu University of Stuttgart

PD Dr. phil. Joachim Wündisch University of Stuttgart

Prof. iR Dr. Günter Wunner University of Stuttgart

 

Other publications of authors with the same name

An ultra low power operated logic NVM for passive UHF RFID tag applications., , , , , and . ICICDT, page 1-4. IEEE, (2016)Stereo Correspondence Using Stripe Adjacency Graph., and . ICPR (1), page 123-126. IEEE Computer Society, (2006)A NoC Simulation and Verification Platform Based on SystemC., , , and . CSSE (3), page 423-426. IEEE Computer Society, (2008)978-0-7695-3336-0.Lottery Router: A Customized Arbitral Priority NOC Router., , , and . CSSE (3), page 411-414. IEEE Computer Society, (2008)978-0-7695-3336-0.An efficient algorithm for performance-optimal FPGA technology mapping with retiming., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 17 (9): 738-748 (1998)Optimal FPGA mapping and retiming with efficient initial state computation., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 18 (11): 1595-1607 (1999)Optimal FPGA Mapping and Retiming with Efficient Initial State Computation., and . DAC, page 330-335. ACM Press, (1998)Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices., , , and . SLIP@DAC, page 1:1-1:8. ACM, (2018)An analytical model for Network-on-Chip with finite input buffer., , and . Frontiers of Computer Science in China, 5 (1): 126-134 (2011)An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig., and . ICCD, page 572-578. IEEE Computer Society, (1996)