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A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing.

, , , and . IEEE Trans. VLSI Syst., 21 (1): 151-156 (2013)

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Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing., , and . IEEE Trans. on Circuits and Systems, 55-II (10): 986-990 (2008)An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS., , , , , and . IEEE Trans. on Circuits and Systems, 58-I (6): 1252-1263 (2011)Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier., , and . IEEE Trans. on Circuits and Systems, 57-I (1): 83-92 (2010)Design and array implementation a cantilever-based non-volatile memory utilizing vibrational reset., , , , , and . ESSDERC, page 284-287. IEEE, (2013)An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving., , , , and . APCCAS, page 704-707. IEEE, (2010)An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS., , , , and . IEEE Trans. VLSI Syst., 27 (1): 126-137 (2019)An Exploratory Study on Websites Quality Assessment., , and . ER Workshops, volume 8697 of Lecture Notes in Computer Science, page 170-179. Springer, (2013)A comparative study of state-of-the-art low-power CAM match-line sense amplifier designs., , , , and . ACM Great Lakes Symposium on VLSI, page 371-374. ACM, (2011)A Backpropagation Extreme Learning Machine Approach to Fast Training Neural Network-Based Side-Channel Attack., , , and . AsianHOST, page 1-6. IEEE, (2021)A hybrid NEO-based spike detection algorithm for implantable brain-IC interface applications., and . ISCAS, page 2393-2396. IEEE, (2014)