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Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device., , , , , and . IEEE Trans. VLSI Syst., 16 (9): 1210-1219 (2008)The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens)., , , , , and . it - Information Technology, 49 (3): 143- (2007)RAR-NoC: A reconfigurable and adaptive routable Network-on-Chip for FPGA-based multiprocessor systems., and . ReConFig, page 1-6. IEEE, (2014)Automatic OpenCL Code Generation from LLVM-IR using Polyhedral Optimization., , and . PARMA-DITAM@HiPEAC, page 45-50. ACM, (2018)Adaptive processor architecture - invited paper., , , , and . ICSAMOS, page 244-251. IEEE, (2012)CAP-OS: Operating system for runtime scheduling, task mapping and resource management on reconfigurable multiprocessor architectures., , , and . IPDPS Workshops, page 1-8. IEEE, (2010)Heterogeneous and runtime parameterizable Star-Wheels Network-on-Chip., , , and . ICSAMOS, page 380-387. IEEE, (2011)New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach., , , and . FPL, page 495-498. IEEE, (2008)Performance, accuracy, power consumption and resource utilization analysis for hardware / software realized Artificial Neural Networks., , , , , and . BIC-TA, page 1629-1636. IEEE, (2010)Scalable clustering and mapping algorithm for application distribution on heterogeneous and irregular FPGA clusters., and . J. Parallel Distrib. Comput., (2019)