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The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator., , and . FPT, page 1-4. IEEE, (2011)Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays., , , , , , and . FPT, page 273-276. IEEE, (2007)A low power reconfigurable accelerator using a back-gate bias control technique., , , and . FPT, page 390-393. IEEE, (2013)A speculative gather system for Cool Mega-Array., , , , , and . FPT, page 346-349. IEEE, (2013)A Thermal Management System for Building Block Computing Systems., , and . MCSoC, page 165-171. IEEE, (2014)A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface., , , , , , , , , and 1 other author(s). IEEE Micro, 33 (6): 6-15 (2013)Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs., , and . ERSA, page 215-221. CSREA Press, (2008)Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot., , , , , , and . PARELEC, page 9-14. IEEE Computer Society, (2002)Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA., , , , , and . CIT, page 567-572. IEEE Computer Society, (2007)On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism., , , , , , and . ISPAN, page 186-194. IEEE Computer Society, (2000)