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Disambiguation of "Shrivastava, Aviral"

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A predictable and command-level priority-based DRAM controller for mixed-criticality systems.

, , , , , and . RTAS, page 317-326. IEEE Computer Society, (2015)

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Other publications of authors with the same name

Operation tables for scheduling in the presence of incomplete bypassing., , , and . CODES+ISSS, page 194-199. ACM, (2004)Smart driver for power reduction in next generation bistable electrophoretic display technology., , and . CODES+ISSS, page 197-202. ACM, (2007)Languages Must Expose Memory Heterogeneity., , , and . MEMSYS, page 251-256. ACM, (2016)Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors., , and . DATE, page 1190-1195. ACM, (2008)Automatic management of Software Programmable Memories in Many-core Architectures., , , , , and . IET Computers & Digital Techniques, 10 (6): 288-298 (2016)An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs., , , , and . DATE, page 402-408. IEEE Computer Society, (2002)Automatic generation of operation tables for fast exploration of bypasses in embedded processors., , , , , and . DATE, page 1197-1202. European Design and Automation Association, Leuven, Belgium, (2006)UnSync: A Soft Error Resilient Redundant Multicore Architecture., , , , and . ICPP, page 632-641. IEEE Computer Society, (2011)Stack data management for Limited Local Memory (LLM) multi-core processors., , and . ASAP, page 231-234. IEEE Computer Society, (2011)WCET-Aware Function-Level Dynamic Code Management on Scratchpad Memory., , and . ACM Trans. Embedded Comput. Syst., 16 (4): 112:1-112:26 (2017)