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Netrace: dependency-driven trace-based network-on-chip simulation.

, , and . NoCArc@MICRO, page 31-36. ACM, (2010)

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A QoS-Enabled On-Die Interconnect Fabric for Kilo-Node Chips., , , and . IEEE Micro, 32 (3): 17-25 (2012)BuMP: Bulk Memory Access Prediction and Streaming., , , and . MICRO, page 545-557. IEEE, (2014)C3D: Mitigating the NUMA bottleneck via coherent DRAM caches., , , , and . MICRO, page 1-12. IEEE Computer Society, (2016)Farewell My Shared LLC! A Case for Private Die-Stacked DRAM Caches for Servers., , , and . MICRO, page 559-572. IEEE Computer Society, (2018)Topology-Aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors., , and . ISCA Workshops, volume 6161 of Lecture Notes in Computer Science, page 357-375. Springer, (2010)Algorithm/Architecture Co-Design for Near-Memory Processing., , , , , , , and . Operating Systems Review, 52 (1): 109-122 (2018)The Mondrian Data Engine., , , , , , , and . ISCA, page 639-651. ACM, (2017)Netrace: dependency-driven trace-based network-on-chip simulation., , and . NoCArc@MICRO, page 31-36. ACM, (2010)Blasting through the Front-End Bottleneck with Shotgun., , and . ASPLOS, page 30-42. ACM, (2018)Scale-out NUMA., , , , and . ASPLOS, page 3-18. ACM, (2014)