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A hardware in the loop design methodology for FPGA system and its application to complex functions.

G. Liang, D. He, J. Portilla, and T. Riesgo. VLSI-DAT, page 1-4. IEEE, (2012)

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Power management techniques in an FPGA-based WSN node for high performance applications.M. Lombardo, J. Camarero, J. Valverde, J. Portilla, E. de la Torre, and T. Riesgo. ReCoSoC, page 1-8. IEEE, (2012)Performance evaluation of an AODV-based routing protocol implementation by using a novel in-field WSN diagnosis tool.G. Mujica, J. Portilla, and T. Riesgo. Microprocessors and Microsystems - Embedded Hardware Design, 39 (8): 920-938 (2015)Edge and Fog Computing Platform for Data Fusion of Complex Heterogeneous Sensors.G. Mujica, R. Rodriguez-Zurrunero, M. Wilby, J. Portilla, A. Rodríguez-González, Á. Araujo, T. Riesgo, and J. Vinagre-Díaz. Sensors, 18 (11): 3630 (2018)FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework.A. Rodríguez, J. Valverde, J. Portilla, A. Otero, T. Riesgo, and E. de la Torre. Sensors, 18 (6): 1877 (2018)Simulation tool and case study for planning wireless sensor network.D. He, G. Mujica, J. Portilla, and T. Riesgo. IECON, page 6024-6028. IEEE, (2012)Hardware-software integration platform for a WSN testbed based on cookies nodes.G. Mujica, V. Rosello, J. Portilla, and T. Riesgo. IECON, page 6013-6018. IEEE, (2012)A novel on-site deployment, commissioning and debugging technique to assess and validate WSN based smart systems.G. Mujica, A. Garcia, J. Gordillo, J. Portilla, and T. Riesgo. ISCAS, page 1722-1725. IEEE, (2015)A Hardware Library for Sensors/Actuators Interfaces in Sensor Networks.J. Portilla, J. Buron, T. Riesgo, and A. de Castro. ICECS, page 1244-1247. IEEE, (2006)Modelling and planning reliable wireless sensor networks based on multi-objective optimization genetic algorithm with changeable length.D. He, G. Mujica, J. Portilla, and T. Riesgo. J. Heuristics, 21 (2): 257-300 (2015)Radio propagation modeling and real test of ZigBee based indoor wireless sensor networks.D. He, G. Mujica, G. Liang, J. Portilla, and T. Riesgo. Journal of Systems Architecture - Embedded Systems Design, 60 (9): 711-725 (2014)

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Disambiguation of "Portilla, Jorge"

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A hardware in the loop design methodology for FPGA system and its application to complex functions.

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Disambiguation of "Portilla, Jorge"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A hardware in the loop design methodology for FPGA system and its application to complex functions.

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A hardware in the loop design methodology for FPGA system and its application to complex functions.