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Disambiguation of "de la Torre, Eduardo"

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FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework.

, , , , , and . Sensors, 18 (6): 1877 (2018)

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Amelia Torres Pareja University of Stuttgart

Edgar Torres University of Stuttgart

Maria Valeria Torres Lopes Rauck University of Stuttgart

Carlos Eduardo Jimenez University of Stuttgart

Jörg Desel

Das ist Informatik (Eds.) Springer, (2001)
 

Other publications of authors with the same name

Automatic generation of identical routing pairs for FPGA implemented DPL logic., , , and . ReConFig, page 1-6. IEEE, (2012)A Modular Peripheral to Support Self-Reconfiguration in SoCs., , , , and . DSD, page 88-95. IEEE Computer Society, (2010)A dynamic communication strategy for the distributed ATPG system DPLATON., , , and . EURO-DAC, page 271-276. IEEE Computer Society, (1993)Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks., , , , , and . Sensors, 12 (3): 2667-2692 (2012)Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems., , , , , and . ReConFig, page 164-169. IEEE Computer Society, (2011)Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion., , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 1057-1061. Springer, (2004)Generic Systolic Array for Run-Time Scalable Cores., , , and . ARC, volume 5992 of Lecture Notes in Computer Science, page 4-16. Springer, (2010)A Progressive Dual-Rail Routing Repair Approach for FPGA Implementation of Crypto Algorithm., , , , , and . ISPEC, volume 8434 of Lecture Notes in Computer Science, page 217-231. Springer, (2014)Distributed Implementation of an ATPG System Using Dynamic Fault Allocation., , , and . ITC, page 409-418. IEEE Computer Society, (1993)Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support., , , , , and . AHS, page 184-191. IEEE, (2011)