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A 42ppm/∘C 0.7V 47nW Low-Complexity All-MOSFET Sub-Threshold Voltage Reference., and . Journal of Circuits, Systems, and Computers, 27 (7): 1850105:1-1850105:8 (2018)A Gain-Tunable Output Buffer for Audio-DAC with Common-Mode Output Independent of Gain Variation., and . Journal of Circuits, Systems, and Computers, 24 (7): 1550106:1-1550106:16 (2015)A 10-Bit 5 MS/s VCO-SAR ADC in 0.18-µm CMOS., , , , and . IEEE Trans. on Circuits and Systems, 66-II (1): 26-30 (2019)An Energy-Efficient Switching Scheme for Low-Power SAR ADC Design., and . Journal of Circuits, Systems, and Computers, 27 (1): 1850015:1-1850015:11 (2018)Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances., , , , , and . IEEE Trans. VLSI Syst., 27 (12): 2855-2860 (2019)Calibration algorithm for 16-bit voltage-mode R-2R DAC., , and . Microelectronics Journal, 46 (10): 963-969 (2015)A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS., , and . Microelectronics Journal, 46 (10): 988-995 (2015)A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18- μm CMOS for Medical Implant Devices., and . IEEE Trans. on Circuits and Systems, 62-I (9): 2167-2176 (2015)Synchronization of Non-Identical Unknown Chaotic Delayed Neural Networks Based on Adaptive Sliding Mode Control., and . Neural Processing Letters, 35 (3): 245-255 (2012)Ultra-low energy switching scheme for SAR ADC., , , and . IEICE Electronic Express, 12 (13): 20150439 (2015)