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A background fast convergence algorithm for timing skew in time-interleaved ADCs., , , and . Microelectronics Journal, (2016)An 8-Bit 0.333-2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS., , , and . Journal of Circuits, Systems, and Computers, 24 (6): 1550093:1-1550093:14 (2015)Radio frequency analog-to-digital converters: Systems and circuits review., , , , , , and . Microelectron. J., (2022)A 10-bit 100-MS/s 5.23-mW SAR ADC in 0.18-μm CMOS., , , , and . Microelectronics Journal, (2018)A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration., , , , , and . IEEE Trans. on Circuits and Systems, 66-II (1): 16-20 (2019)A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS., , , and . Journal of Circuits, Systems, and Computers, 25 (8): 1650084:1-1650084:11 (2016)A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS., , , and . IEEE Trans. on Circuits and Systems, 65-II (11): 1524-1528 (2018)A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration., , , , , and . CICC, page 1-4. IEEE, (2019)A Background Timing Skew Calibration Technique in Time-Interleaved ADCs With Second Order Compensation., , , and . APCCAS, page 53-56. IEEE, (2018)