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Memory aspects in signal processing and HLS tool: Some results., , , and . EUSIPCO, page 1-4. IEEE, (1996)Asynchronous timing model for high-level synthesis of DSP applications., , and . EUSIPCO, page 1-4. IEEE, (1998)DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints., , , and . IPDPS, IEEE Computer Society, (2002)Parallelism Level Impact on Energy Consumption in Reconfigurable Devices., , , and . SIGARCH Computer Architecture News, 39 (4): 104-105 (2011)A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals., , , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 51-62. Kluwer, (2001)VLSI high level synthesis of fast exact least mean square algorithms based on fast FIR filters., , , and . ICASSP, page 671-674. IEEE Computer Society, (1997)Power consumption model for partial and dynamic reconfiguration., , , and . ReConFig, page 1-8. IEEE, (2012)Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures., , , , and . Int. J. Reconfig. Comp., (2010)Approximate nanophotonic interconnects., , , and . NOCS, page 9:1-9:7. ACM, (2019)R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip., , , and . ReConFig, page 376-381. IEEE Computer Society, (2010)