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Disambiguation of "Crupi, Felice"

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Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs.

, , , , , , , , , , and . ESSDERC, page 330-333. IEEE, (2012)

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Other publications of authors with the same name

Experimental study of leakage-delay trade-off in Germanium pMOSFETs for logic circuits., , , and . ISCAS, page 1699-1702. IEEE, (2010)A portable class of 3-transistor current references with low-power sub-0.5 V operation., , , , , and . I. J. Circuit Theory and Applications, 46 (4): 779-795 (2018)A picopower temperature-compensated, subthreshold CMOS voltage reference., , , and . I. J. Circuit Theory and Applications, 42 (12): 1306-1318 (2014)Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework., , , , , and . SMACD, page 1-4. IEEE, (2017)Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs., , , , , , and . SMACD, page 85-88. IEEE, (2019)Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions., , , , , and . IDCS, volume 11874 of Lecture Notes in Computer Science, page 294-305. Springer, (2019)Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires., , , , and . ESSDERC, page 282-285. IEEE, (2014)Full Model and Characterization of Noise in Operational Amplifier., , , and . IEEE Trans. on Circuits and Systems, 56-I (1): 97-102 (2009)A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference., , , , and . J. Solid-State Circuits, 46 (2): 465-474 (2011)Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines., , , and . I. J. Circuit Theory and Applications, 43 (11): 1523-1540 (2015)