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A 28 nm 0.6 V Low Power DSP for Mobile Applications.

N. Ickes, G. Gammie, M. Sinangil, R. Rithe, J. Gu, A. Wang, H. Mair, S. Datla, B. Rong, S. Prasad, L. Ho, G. Baldwin, D. Buss, A. Chandrakasan, and U. Ko. J. Solid-State Circuits, 47 (1): 35-46 (2012)

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Solutions for logic and processor core design at the 45nm technology node & and below.P. Royannez, H. Mair, M. Clinton, and U. Ko. ICECS, page 923-926. IEEE, (2007)A 28 nm 0.6 V Low Power DSP for Mobile Applications.N. Ickes, G. Gammie, M. Sinangil, R. Rithe, J. Gu, A. Wang, H. Mair, S. Datla, B. Rong, S. Prasad and 5 other author(s). J. Solid-State Circuits, 47 (1): 35-46 (2012)A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques.G. Gammie, A. Wang, M. Chau, S. Gururajarao, R. Pitts, F. Jumel, S. Engel, P. Royannez, R. Lagerquist, H. Mair and 7 other author(s). ISSCC, page 258-259. IEEE, (2008)4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance.H. Mair, G. Gammie, A. Wang, R. Lagerquist, C. Chung, S. Gururajarao, P. Kao, A. Rajagopalan, A. Saha, A. Jain and 19 other author(s). ISSCC, page 76-77. IEEE, (2016)Session 17 overview: SRAM.H. Mair, and A. Kawasumi. ISSCC, page 304-305. IEEE, (2016)A 28nm 0.6V low-power DSP for mobile applications.G. Gammie, N. Ickes, M. Sinangil, R. Rithe, J. Gu, A. Wang, H. Mair, S. Datla, B. Rong, S. Prasad and 5 other author(s). ISSCC, page 132-134. IEEE, (2011)Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver.A. Joy, H. Mair, H. Lee, A. Feldman, C. Portmann, N. Bulman, E. Crespo, P. Hearne, P. Huang, B. Kerr and 10 other author(s). ISSCC, page 350-351. IEEE, (2011)A design platform for 90-nm leakage reduction techniques.P. Royannez, H. Mair, F. Dahan, M. Wagner, M. Streeter, L. Bouetel, J. Blasquez, H. Clasen, G. Semino, J. Dong and 4 other author(s). DAC, page 549-550. ACM, (2005)SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors.G. Gammie, A. Wang, H. Mair, R. Lagerquist, M. Chau, P. Royannez, S. Gururajarao, and U. Ko. Proceedings of the IEEE, 98 (2): 144-159 (2010)A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V.M. Sinangil, H. Mair, and A. Chandrakasan. ISSCC, page 260-262. IEEE, (2011)

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A 28 nm 0.6 V Low Power DSP for Mobile Applications.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 28 nm 0.6 V Low Power DSP for Mobile Applications.

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A 28 nm 0.6 V Low Power DSP for Mobile Applications.