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Impact of on-chip network parameters on nuca cache performances.

, , , , and . IET Computers & Digital Techniques, 3 (5): 501-512 (2009)

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Performance Sensitivity of NUCA Caches to On-Chip Network Parameters., , , , and . SBAC-PAD, page 167-174. IEEE Computer Society, (2008)The ARM Scalable Vector Extension., , , , , , , , , and 3 other author(s). CoRR, (2018)Improving power efficiency of D-NUCA caches., , , , and . SIGARCH Computer Architecture News, 35 (4): 53-58 (2007)Advanced SIMD: Extending the reach of contemporary SIMD architectures., , , , and . DATE, page 1-4. European Design and Automation Association, (2014)Leveraging Data Promotion for Low Power D-NUCA Caches., , , , , and . DSD, page 307-316. IEEE Computer Society, (2008)A power-efficient migration mechanism for D-NUCA caches., , , , and . DATE, page 598-601. IEEE, (2009)Way adaptable D-NUCA caches., , , , and . IJHPSA, 2 (3/4): 215-228 (2010)Impact of on-chip network parameters on nuca cache performances., , , , and . IET Computers & Digital Techniques, 3 (5): 501-512 (2009)The ARM Scalable Vector Extension., , , , , , , , , and 3 other author(s). IEEE Micro, 37 (2): 26-39 (2017)MALEC: a multiple access low energy cache., , , and . DATE, page 368-373. EDA Consortium San Jose, CA, USA / ACM DL, (2013)