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Impact of on-chip network parameters on nuca cache performances.

, , , , and . IET Computers & Digital Techniques, 3 (5): 501-512 (2009)

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Improving power efficiency of D-NUCA caches., , , , and . SIGARCH Computer Architecture News, 35 (4): 53-58 (2007)Analysis of embedded video coder systems: a system-level approach., , , and . SIGARCH Computer Architecture News, 34 (1): 71-76 (2006)Energy Behaviour of NUCA Caches in CMPs., , , , and . DSD, page 746-753. IEEE Computer Society, (2011)Performance Sensitivity of NUCA Caches to On-Chip Network Parameters., , , , and . SBAC-PAD, page 167-174. IEEE Computer Society, (2008)NURBS interpolator with confined chord error and tangential and centripetal acceleration control., , , and . ICUMT, page 489-496. IEEE, (2010)A real-time configurable NURBS interpolator with bounded acceleration, jerk and chord error., , , , and . Computer-Aided Design, 44 (6): 509-521 (2012)Evaluation of Leakage Reduction Alternatives for Deep Submicron Dynamic Nonuniform Cache Architecture Caches., , , and . IEEE Trans. VLSI Syst., 22 (1): 185-190 (2014)Analysis of static and dynamic energy consumption in NUCA caches: initial results., , , and . MEDEA@PACT, page 105-112. ACM, (2007)Way adaptable D-NUCA caches., , , , and . IJHPSA, 2 (3/4): 215-228 (2010)Impact of on-chip network parameters on nuca cache performances., , , , and . IET Computers & Digital Techniques, 3 (5): 501-512 (2009)