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Disambiguation of "Gonugondla, Sujan K."

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Energy-Efficient Deep In-memory Architecture for NAND Flash Memories.

, , , , , and . ISCAS, page 1-5. IEEE, (2018)

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K. Stahl

K. Gaiser

K. Lindow

Grzegorz K. Karch

Dipl.-Ing. Thomas Kuestner

Scan time reduction in DWI of the pancreas using simultaneous multislice technique with different acceleration factors: how fast can we go?, , , , , , , and . Proceedings of the International Society for Magnetic Resonance in Medicine (ISMRM), Honolulu, Hawaii, USA, (April 2017)
 

Other publications of authors with the same name

An MRAM-Based Deep In-Memory Architecture for Deep Neural Networks., , , , and . ISCAS, page 1-5. IEEE, (2019)A 481pJ/decision 3.4M decision/s Multifunctional Deep In-memory Inference Processor using Standard 6T SRAM Array., , , and . CoRR, (2016)PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms., , , , , , , and . ISCA, page 43-56. IEEE Computer Society, (2018)Perfect error compensation via algorithmic error cancellation., , and . ICASSP, page 966-970. IEEE, (2016)Energy-Efficient Deep In-memory Architecture for NAND Flash Memories., , , , , and . ISCAS, page 1-5. IEEE, (2018)A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training., , and . J. Solid-State Circuits, 53 (11): 3163-3173 (2018)An In-Memory VLSI Architecture for Convolutional Neural Networks., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 494-505 (2018)An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks., , , and . ICASSP, page 1037-1041. IEEE, (2015)A 19.4 nJ/decision 364K decisions/s in-memory random forest classifier in 6T SRAM array., , and . ESSCIRC, page 263-266. IEEE, (2017)