PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Kang, Mingu"

Author of the publication

copydeleteadd this publication to your clipboard
An In-Memory VLSI Architecture for Convolutional Neural Networks.

, , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 494-505 (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

M.Sc Yeonse Kang University of Stuttgart

 

Other publications of authors with the same name

Serial-Parallel Content Addressable Memory with a Conditional Driver (SPCwCD)., and . IEICE Transactions, 92-A (1): 318-321 (2009)Supply chain integration and coordination for international sourcing in the context of China's processing trade., , , and . Industrial Management and Data Systems, 118 (9): 1730-1748 (2018)In-Memory Computing Architectures for Sparse Distributed Memory., and . IEEE Trans. Biomed. Circuits and Systems, 10 (4): 855-863 (2016)Energy-Efficient Deep In-memory Architecture for NAND Flash Memories., , , , , and . ISCAS, page 1-5. IEEE, (2018)FamCom: A Communication Service Enhancing Conversation Quality Between Elders Residing in Care Hospital and Their Family Member., , , and . CHI Extended Abstracts, page 13-18. ACM, (2015)The effects of socio-technical integration on sustainability practices: a supply chain perspective., , , and . Ind. Manag. Data Syst., 122 (2): 419-441 (2022)CAP-GAN: Towards Adversarial Robustness with Cycle-consistent Attentional Purification., , , and . CoRR, (2021)PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms., , , , , , , and . ISCA, page 43-56. IEEE Computer Society, (2018)A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training., , and . J. Solid-State Circuits, 53 (11): 3163-3173 (2018)An In-Memory VLSI Architecture for Convolutional Neural Networks., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 494-505 (2018)