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Low power tri-state register files design for modern out-of-order processors., , , and . SoCC, page 323-328. IEEE, (2011)Optimization and predication of leakage current characteristics in wide domino OR gates under PVT variation., and . SoCC, page 19-24. IEEE, (2010)Mitigating Nonlinear Effect of Memristive Synaptic Device for Neuromorphic Computing., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 9 (2): 377-387 (2019)A thermal-aware distribution method of TSV in 3D IC., , , , , and . ASICON, page 1-3. IEEE, (2015)Novel CMOS technology compatible nonvolatile on-chip hybrid memory., , , and . ASICON, page 1-4. IEEE, (2015)Dummy TSV based bit-line optimization in 3D on-chip memory., , , , and . EIT, page 580-585. IEEE, (2016)TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors., , , and . IEEE Trans. VLSI Syst., 23 (7): 1196-1209 (2015)Fan-in sensitive low power dynamic circuits performance statistical characterization., , , and . SoCC, page 321-325. IEEE, (2010)Switching and leakage power modeling for multiple-supply dynamic gate with delay constraining based on wavelet neural networks., , , , , , , and . IJCNN, page 3240-3243. IEEE Computer Society, (2009)Data-Pattern enabled Self-Recovery multimedia storage system for near-threshold computing., , , and . ICCD, page 492-498. IEEE Computer Society, (2016)