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Disambiguation of "Biswas, Partha"

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ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement.

, , , , and . DATE, page 1246-1251. IEEE Computer Society, (2005)

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Ananya Biswas University of Stuttgart

 

Other publications of authors with the same name

Automatic identification of application-specific functional units with architecturally visible storage., , , and . DATE, page 212-217. European Design and Automation Association, Leuven, Belgium, (2006)An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs., , , , and . DATE, page 402-408. IEEE Computer Society, (2002)ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors., , , , and . IEEE Trans. VLSI Syst., 14 (7): 754-762 (2006)Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions., and . CASES, page 104-112. ACM, (2003)Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions., and . IEEE Trans. Computers, 54 (10): 1216-1226 (2005)Introduction of Architecturally Visible Storage in Instruction Set Extensions., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (3): 435-446 (2007)Introduction of local memory elements in instruction set extensions., , , , , and . DAC, page 729-734. ACM, (2004)A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design ., , , , and . ISSS, page 120-125. ACM / IEEE Computer Society, (2002)ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement., , , , and . DATE, page 1246-1251. IEEE Computer Society, (2005)Compilation framework for code size reduction using reduced bit-width ISAs (rISAs)., , , , and . ACM Trans. Design Autom. Electr. Syst., 11 (1): 123-146 (2006)